Cisco is hiring Fresher’s Graduate’s for the Role of ASIC Design Verification Engineer. Any Graduate’s can Apply for this Position.
Cisco Recruitment Drive Details:
| Role | ASIC Design Verification Engineer |
| Qualification | Graduate or Master (Preferred) |
| Batch | 2017, 2018, 2019, 2020 & 2021 |
| Salary | ₹ 6-8 LPA Expected |
| Job Location | Across, India |
| Last Date | ASAP |
| Experience | 1 to 4 Exp. |
What You’ll Do :
Cisco SiliconOne team is looking for a talented and a dynamic design verification engineer. You will have an ASIC background with hands-on experience in design verification, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
Responsibilities :
- Looking for a Front-end Design Verification Engineer.
- Work in verification environment architecture keeping reusability in mind.
- Writing tests, automate/speed up env/tests by code gens/scripts
Who You Are :
- Worked in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components using UVM.
- Problem solving skills and out-of-the-box thinking at reusing SV (UVM) classes for the verification and simulation environments.
- Experience in writing thorough test plans as well as oral descriptions.
- BSEE is required /MSEE is preferred.
- Team-player, can-do attitude will work well in a group environment while still being able to contribute on an individual basis and you will find that you’ll have lots of fun and thrive in this environment if you enjoy being challenged, learning new ideas, and push yourself to achieve aggressive technology goals.
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Minimum Qualifications :
- Must be a recent graduate from a premier institute and working for a reputed product or semiconductor company
- Experience in coding tests/small verification envs.
- Verification tools/Languages/methodologies (VCS, System Verilog, UVM/OVM, Formal verification)
- Experienced in debugging aids/tools.
- Programming/scripting skills (C, C++, Perl)
- Work experience of BSEE+5/MSEE+3 years
- Good written/verbal interpersonal skills and leadership skills.
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